ARM supports indirect and pre and post-indexed addressing modes, PC-relative addressing for position independent code, and more. The compiler output showed the use of indirect addressing using the frame pointer. I would like to mention some topics that you might want to explore in more detail.Īddressing modes: We didn't cover the supported instruction addressing modes. There are many more ARM instructions and features that we could cover, but not in a reasonable length for a blog post. Str r1, tmp115, j Advanced and Miscellaneous Topics Arithmetic shifts maintain the sign of the value. The operations are LSL, LSR, ASL, ASR, ROR, ROL, RRX (rotate through extend/carry bit).
This is supported by instructions for move, add, subtract, compare, and, or, xor, test, and others. The shift or rotate operation is added as an optional third operand. Shifts and rotates are only done as part of other instructions and not explicitly with shift or rotate instructions (however, the assembler will accept them as instructions and convert them to a MOV). The ARM CPU has a barrel shifter that can shift or rotate a result by up to 32 bit positions at once. The conditions supported are the following: EQ/NE MOV CS R0,R1 Same as above (space allowed between mnemonic and condition )
